aboutsummaryrefslogtreecommitdiffstats
path: root/README.md
Commit message (Collapse)AuthorAgeFilesLines
* Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-021-0/+3
| | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* README: explain how to do out-of-tree builds.whitequark2020-04-241-1/+8
|
* ast/simplify: improve enum handling.whitequark2020-04-151-2/+2
| | | | | | | | | | | | | | | | | | | | | Before this commit, enum values were serialized as attributes of form \enum_<width>_<value> where <value> was a decimal signed integer. This has multiple drawbacks: * Enums with large values would be hard to process for downstream tooling that cannot parse arbitrary precision decimals. (In fact Yosys also did not correctly process enums with large values, and would overflow `int`.) * Enum value attributes were not confined to their own namespace, making it harder for downstream tooling to enumerate all such attributes, as opposed to looking up any specific value. * Enum values could not include x or z, which are explicitly permitted in the SystemVerilog standard. After this commit, enum values are serialized as attributes of form \enum_value_<value> where <value> is a bit sequence of the appropriate width.
* Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-231-2/+0
|
* Update CopyrightClaire Wolf2020-03-161-1/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* License: bump year and add titleWaldir Pimenta2020-03-141-1/+1
|
* Small fixesEddie Hung2020-02-271-6/+6
|
* xilinx: improve specify functionalityEddie Hung2020-02-271-1/+6
|
* xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-13/+2
|
* Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-0/+17
|\ | | | | Enum support
| * update documentation for enums and typedefsJeff Wang2020-02-171-0/+17
| |
* | Add comment for macOS dependency installMiodrag Milanović2020-02-151-1/+1
| |
* | Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-051-4/+9
|\ \ | | | | | | abc9: add support for required times
| * | Fix typoEddie Hung2020-01-271-1/+1
| | |
| * | Update README.md for (* abc9_required *)Eddie Hung2020-01-151-4/+9
| |/
* / Update CHANGELOG and READMEDavid Shah2020-02-021-0/+4
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Reword (* abc9_flop *) descriptionEddie Hung2020-01-061-2/+3
|
* Restore abc9 -keepffEddie Hung2020-01-011-3/+0
|
* Add CHANGELOG entry, add abc9_{flop,keep} attr to README.mdEddie Hung2019-12-301-0/+6
|
* Put specify/endspecify inside ``Eddie Hung2019-12-201-4/+4
|
* Update README.md :: abc_ -> abc9_Eddie Hung2019-12-111-3/+3
|
* clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-0/+7
|
* Update CHANGELOG and READMEDavid Shah2019-11-221-0/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Update CHANGELOG and READMEDavid Shah2019-10-031-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Added extractinv passMarcin Kościelnicki2019-09-191-0/+6
|
* Merge pull request #1312 from YosysHQ/xaig_arrivalEddie Hung2019-09-051-8/+5
|\ | | | | Allow arrival times of sequential outputs to be specified to abc9
| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-14/+14
| |\
| * \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-1/+1
| |\ \
| * \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-281-0/+15
| |\ \ \
| * \ \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-231-3/+6
| |\ \ \ \
| * | | | | Add (* abc_arrival=<int> *) docEddie Hung2019-08-201-0/+5
| | | | | |
| * | | | | Deprecate `abc_scc_break` attributeEddie Hung2019-08-201-8/+0
| | | | | |
* | | | | | Update README.mdClifford Wolf2019-09-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes ↵Clifford Wolf2019-09-051-0/+3
| |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | #1220 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #1340 from YosysHQ/eddie/abc_no_cleanEddie Hung2019-08-301-17/+17
|\ \ \ \ \ | |_|_|_|/ |/| | | | abc9 to not call "clean" at end of run (often called outside)
| * | | | Group abc_* attribute doc with other attributesEddie Hung2019-08-291-17/+17
| | |_|/ | |/| |
* / | | Format `-pwires`Eddie Hung2019-08-301-1/+1
|/ / /
* | | Mention clkbuf_inhibit can be overriddenEddie Hung2019-08-231-7/+8
| | |
* | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-3/+23
|\ \ \ | | |/ | |/|
| * | Make macOS depenency clearMiodrag Milanovic2019-08-231-2/+5
| | |
| * | Bump year in copyright noticeClifford Wolf2019-08-221-1/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Clarify with 'only'Eddie Hung2019-08-191-1/+1
| |
| * Update docEddie Hung2019-08-191-3/+4
| |
| * Add doc for abc_* attributesEddie Hung2019-08-161-0/+16
| |
* | README updatesMarcin Kościelnicki2019-08-131-0/+14
|/
* Update README to use "read" instead of "read_verilog"Clifford Wolf2019-07-291-48/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for reading gzip'd input filesDavid Shah2019-07-261-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Updated FreeBSD dependencies in README.mdRoman-Parise2019-07-141-1/+1
|
* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add defaultvalue attributeClifford Wolf2019-06-191-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 13:37:31 +0000