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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 15:10:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 15:10:01 -0700 |
| commit | 0ca397f087287307d13daac57f60c24c6f2a982e (patch) | |
| tree | 211921951876079649ad96b602802d5326c1d451 /README.md | |
| parent | e273ed52758599cb156cf3c309905da70826fe2d (diff) | |
| download | yosys-0ca397f087287307d13daac57f60c24c6f2a982e.tar.gz yosys-0ca397f087287307d13daac57f60c24c6f2a982e.tar.bz2 yosys-0ca397f087287307d13daac57f60c24c6f2a982e.zip | |
Deprecate `abc_scc_break` attribute
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 8 |
1 files changed, 0 insertions, 8 deletions
@@ -409,14 +409,6 @@ Verilog Attributes and non-standard features blackbox or whitebox definition to a corresponding entry in a `abc9` box-file. -- The port attribute ``abc_scc_break`` indicates a module input port that will - be treated as a primary output during `abc9` techmapping. Doing so eliminates - the possibility of a strongly-connected component (i.e. a combinatorial loop) - existing. Typically, this is specified for sequential inputs on otherwise - combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D` - port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths - as a combinatorial loop. - - The port attribute ``abc_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for `abc9` to preserve the integrity of carry-chains. Specifying this attribute |