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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 10:32:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 10:32:58 -0700 |
| commit | d87a6f6303194e2af0f9766185fa491077709a7b (patch) | |
| tree | 35a193edd54a29a2f827b8b1e9f84d2b360eb32b /README.md | |
| parent | d2d2816f8cc8703812eb5eb9536c1f3fe1876347 (diff) | |
| parent | 36e38ed46ae4b24be7b627a21a6627437db1ec61 (diff) | |
| download | yosys-d87a6f6303194e2af0f9766185fa491077709a7b.tar.gz yosys-d87a6f6303194e2af0f9766185fa491077709a7b.tar.bz2 yosys-d87a6f6303194e2af0f9766185fa491077709a7b.zip | |
Merge remote-tracking branch 'origin/master' into xaig_arrival
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -330,7 +330,7 @@ Verilog Attributes and non-standard features - The ``parameter`` and ``localparam`` attributes are used to mark wires that represent module parameters or localparams (when the HDL front-end - is run in -pwires mode). + is run in ``-pwires`` mode). - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` |