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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-19 14:38:50 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-06-19 14:38:50 +0200 |
| commit | ec4565009ae69409eb01f1b595f5f59fcc969ce2 (patch) | |
| tree | e4fa22a4a4598e86f0fa324741fb6062dca851e8 /README.md | |
| parent | 5a1f1caa44fb3f4427813acab61aaecc06bae7ba (diff) | |
| download | yosys-ec4565009ae69409eb01f1b595f5f59fcc969ce2.tar.gz yosys-ec4565009ae69409eb01f1b595f5f59fcc969ce2.tar.bz2 yosys-ec4565009ae69409eb01f1b595f5f59fcc969ce2.zip | |
Add "read_verilog -pwires" feature, closes #1106
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -354,6 +354,10 @@ Verilog Attributes and non-standard features module inputs. The attribute is attached to the input wire by the HDL front-end when the input is declared with a default value. +- The ``parameter`` and ``localparam`` attributes are used to mark wires + that represent module parameters or localparams (when the HDL front-end + is run in -pwires mode). + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset |