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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-12 15:25:30 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 12d70ca8fbad73f2615e711e786f8b90fa005bee (patch) | |
| tree | 6459527e212b6e0ac65d99ad023606b6afd5e9f4 /README.md | |
| parent | 46a89d7264f597be9ad10390fa44c22e16538548 (diff) | |
| download | yosys-12d70ca8fbad73f2615e711e786f8b90fa005bee.tar.gz yosys-12d70ca8fbad73f2615e711e786f8b90fa005bee.tar.bz2 yosys-12d70ca8fbad73f2615e711e786f8b90fa005bee.zip | |
xilinx: improve specify functionality
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 7 |
1 files changed, 6 insertions, 1 deletions
@@ -364,8 +364,13 @@ Verilog Attributes and non-standard features it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. +- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9` + that this module describes a LUT with propagation delays described using + `specify` statements. + - The module attribute ``abc9_box`` is a boolean specifying a blackbox or - whitebox definition for use by `abc9`. + whitebox definition, with propagation delays described using `specify` + statements, for use by `abc9`. - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for |