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authorEddie Hung <eddie@fpgeh.com>2019-08-29 12:13:52 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-29 12:13:52 -0700
commitc52db44f9ab19194dbdefd35bd697ab99650f510 (patch)
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Group abc_* attribute doc with other attributes
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1 files changed, 17 insertions, 17 deletions
diff --git a/README.md b/README.md
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@@ -347,6 +347,23 @@ Verilog Attributes and non-standard features
it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
from inserting another pad cell on it.
+- The module attribute ``abc_box_id`` specifies a positive integer linking a
+ blackbox or whitebox definition to a corresponding entry in a `abc9`
+ box-file.
+
+- The port attribute ``abc_scc_break`` indicates a module input port that will
+ be treated as a primary output during `abc9` techmapping. Doing so eliminates
+ the possibility of a strongly-connected component (i.e. a combinatorial loop)
+ existing. Typically, this is specified for sequential inputs on otherwise
+ combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D`
+ port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths
+ as a combinatorial loop.
+
+- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
+ carry-out (if output port) ports of a box. This information is necessary for
+ `abc9` to preserve the integrity of carry-chains. Specifying this attribute
+ onto a bus port will affect only its most significant bit.
+
- In addition to the ``(* ... *)`` attribute syntax, Yosys supports
the non-standard ``{* ... *}`` attribute syntax to set default attributes
for everything that comes after the ``{* ... *}`` statement. (Reset
@@ -423,23 +440,6 @@ Verilog Attributes and non-standard features
blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
functionality. (By default specify .. endspecify blocks are ignored.)
-- The module attribute ``abc_box_id`` specifies a positive integer linking a
- blackbox or whitebox definition to a corresponding entry in a `abc9`
- box-file.
-
-- The port attribute ``abc_scc_break`` indicates a module input port that will
- be treated as a primary output during `abc9` techmapping. Doing so eliminates
- the possibility of a strongly-connected component (i.e. a combinatorial loop)
- existing. Typically, this is specified for sequential inputs on otherwise
- combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D`
- port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths
- as a combinatorial loop.
-
-- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
- carry-out (if output port) ports of a box. This information is necessary for
- `abc9` to preserve the integrity of carry-chains. Specifying this attribute
- onto a bus port will affect only its most significant bit.
-
Non-standard or SystemVerilog features for formal verification
==============================================================