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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-01 08:34:43 -0800 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-01 08:34:43 -0800 |
| commit | c40b1aae42c91f200194f7f5f2caa512787ed5a3 (patch) | |
| tree | cc34ef4e6469c0e310479711c39e5c5ebee39830 /README.md | |
| parent | ac808c5e2aa0fbcfb5b56160131fcc61ba13da05 (diff) | |
| download | yosys-c40b1aae42c91f200194f7f5f2caa512787ed5a3.tar.gz yosys-c40b1aae42c91f200194f7f5f2caa512787ed5a3.tar.bz2 yosys-c40b1aae42c91f200194f7f5f2caa512787ed5a3.zip | |
Restore abc9 -keepff
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 0 insertions, 3 deletions
@@ -381,9 +381,6 @@ Verilog Attributes and non-standard features - The module attribute ``abc9_flop`` is a boolean marking the module as a whitebox that describes the synchronous behaviour of a flip-flop. -- The cell attribute ``abc9_keep`` is a boolean indicating that this black/ - white box should be preserved through `abc9` mapping. - - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks according to the type of the always. These are checked for correctness in |