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author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:24:58 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:24:58 -0800 |
commit | ece423415cbc17654c6ac81a0f4b15783c558660 (patch) | |
tree | daf9eb1e7a3198d0ec25ca4478d9d788f9535261 /README.md | |
parent | a038294a87b44a8eadfb62453f1fd76eec5a04ef (diff) | |
download | yosys-ece423415cbc17654c6ac81a0f4b15783c558660.tar.gz yosys-ece423415cbc17654c6ac81a0f4b15783c558660.tar.bz2 yosys-ece423415cbc17654c6ac81a0f4b15783c558660.zip |
Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -378,6 +378,12 @@ Verilog Attributes and non-standard features for example, to specify the clk-to-Q delay of a flip-flop for consideration during techmapping. +- The module attribute ``abc9_flop`` is a boolean marking the module as a + whitebox that describes the synchronous behaviour of a flip-flop. + +- The cell attribute ``abc9_keep`` is a boolean indicating that this black/ + white box should be preserved through `abc9` mapping. + - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks according to the type of the always. These are checked for correctness in |