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| author | Peter Crozier <peter@crozier.com> | 2020-03-23 20:07:22 +0000 |
|---|---|---|
| committer | Peter Crozier <peter@crozier.com> | 2020-03-23 20:07:22 +0000 |
| commit | ecc22f7fedfa639482dbc55a05709da85116a60f (patch) | |
| tree | f69ecdf848e4c3faa03552e5ef3ddca22fe8cb9e /README.md | |
| parent | b86905d9523767bccc9224ce33a0b51265e4950c (diff) | |
| download | yosys-ecc22f7fedfa639482dbc55a05709da85116a60f.tar.gz yosys-ecc22f7fedfa639482dbc55a05709da85116a60f.tar.bz2 yosys-ecc22f7fedfa639482dbc55a05709da85116a60f.zip | |
Support module/package/interface/block scope for typedef names.
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 0 insertions, 2 deletions
@@ -541,8 +541,6 @@ from SystemVerilog: SystemVerilog files being read into the same design afterwards. - typedefs are supported (including inside packages) - - type identifiers must currently be enclosed in (parentheses) when declaring - signals of that type (this is syntactically incorrect SystemVerilog) - type casts are currently not supported - enums are supported (including inside packages) |