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| author | whitequark <whitequark@whitequark.org> | 2020-04-24 18:07:13 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-24 23:27:43 +0000 |
| commit | 9b26a1fa89e34af8651af381d88088b738c75769 (patch) | |
| tree | 2c94acf61bb3ac837aa02dcdea4a70a034d9e391 /README.md | |
| parent | f1087b2552b73c243be8e37aa69c8511c10745a5 (diff) | |
| download | yosys-9b26a1fa89e34af8651af381d88088b738c75769.tar.gz yosys-9b26a1fa89e34af8651af381d88088b738c75769.tar.bz2 yosys-9b26a1fa89e34af8651af381d88088b738c75769.zip | |
README: explain how to do out-of-tree builds.
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 9 |
1 files changed, 8 insertions, 1 deletions
@@ -118,6 +118,13 @@ Tests are located in the tests subdirectory and can be executed using the test t $ make test +To use a separate (out-of-tree) build directory, provide a path to the Makefile. + + $ mkdir build; cd build + $ make -f ../Makefile + +Out-of-tree builds require a clean source tree. + Getting Started =============== @@ -388,7 +395,7 @@ Verilog Attributes and non-standard features - The cell attribute ``wildcard_port_conns`` represents wildcard port connections (SystemVerilog ``.*``). These are resolved to concrete - connections to matching wires in ``hierarchy``. + connections to matching wires in ``hierarchy``. - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes |