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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 18:59:40 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-05 18:59:40 +0100 |
| commit | 0671ae7d79ead3f7c109ed41ea7ad5e5767f418a (patch) | |
| tree | eff88fad0d90d4a6fd92c6ebda512d5bc010dc2b /README.md | |
| parent | 34d2fbd2f96a8789aa7eb655318308e11949eb7a (diff) | |
| parent | 21ce1b37fbc93562942c10f631c7f415f8fdba2e (diff) | |
| download | yosys-0671ae7d79ead3f7c109ed41ea7ad5e5767f418a.tar.gz yosys-0671ae7d79ead3f7c109ed41ea7ad5e5767f418a.tar.bz2 yosys-0671ae7d79ead3f7c109ed41ea7ad5e5767f418a.zip | |
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 13 |
1 files changed, 9 insertions, 4 deletions
@@ -373,10 +373,15 @@ Verilog Attributes and non-standard features `abc9` to preserve the integrity of carry-chains. Specifying this attribute onto a bus port will affect only its most significant bit. -- The port attribute ``abc9_arrival`` specifies an integer (for output ports - only) to be used as the arrival time of this sequential port. It can be used, - for example, to specify the clk-to-Q delay of a flip-flop for consideration - during `abc9` techmapping. +- The output port attribute ``abc9_arrival`` specifies an integer, or a string + of space-separated integers to be used as the arrival time of this blackbox + port. It can be used, for example, to specify the clk-to-Q delay of a flip- + flop output for consideration during `abc9` techmapping. + +- The input port attribute ``abc9_required`` specifies an integer, or a string + of space-separated integers to be used as the required time of this blackbox + port. It can be used, for example, to specify the setup-time of a flip-flop + input for consideration during `abc9` techmapping. - The module attribute ``abc9_flop`` is a boolean marking the module as a flip-flop. This allows `abc9` to analyse its contents in order to perform |