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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:19:10 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:19:10 -0700 |
commit | 8d820a9884c0a58ee7817a2052d8b915578a7ba7 (patch) | |
tree | 7868bc0063dd0d36aa84a48c8ede1a3f3a8c37c3 /README.md | |
parent | 3fa826254fb337e39334c8d94df6bcc142d17934 (diff) | |
parent | fc727fa5c9e0a04a5dc1b4fcef652c5bca90b220 (diff) | |
download | yosys-8d820a9884c0a58ee7817a2052d8b915578a7ba7.tar.gz yosys-8d820a9884c0a58ee7817a2052d8b915578a7ba7.tar.bz2 yosys-8d820a9884c0a58ee7817a2052d8b915578a7ba7.zip |
Merge remote-tracking branch 'origin/master' into xaig_arrival
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 15 |
1 files changed, 15 insertions, 0 deletions
@@ -332,6 +332,21 @@ Verilog Attributes and non-standard features that represent module parameters or localparams (when the HDL front-end is run in -pwires mode). +- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox + module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` + from inserting another clock buffer on a net driven by such output. + +- The ``clkbuf_sink`` attribute can be set on an input port of a module to + request clock buffer insertion by the ``clkbufmap`` pass. + +- The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent + automatic clock buffer insertion by ``clkbufmap``. This behaviour can be + overridden by providing a custom selection to ``clkbufmap``. + +- The ``iopad_external_pin`` attribute on a blackbox module's port marks + it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` + from inserting another pad cell on it. + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset |