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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-15 14:42:00 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-15 14:42:00 -0800 |
| commit | 168c9d5871e331341058b026cf9b4f6a99a0f759 (patch) | |
| tree | 8837c70b07f7f3ac10d052ab536559a765d22f0b /README.md | |
| parent | 5a63c197477d59567424faab3b56329c426394b9 (diff) | |
| download | yosys-168c9d5871e331341058b026cf9b4f6a99a0f759.tar.gz yosys-168c9d5871e331341058b026cf9b4f6a99a0f759.tar.bz2 yosys-168c9d5871e331341058b026cf9b4f6a99a0f759.zip | |
Update README.md for (* abc9_required *)
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 13 |
1 files changed, 9 insertions, 4 deletions
@@ -373,10 +373,15 @@ Verilog Attributes and non-standard features `abc9` to preserve the integrity of carry-chains. Specifying this attribute onto a bus port will affect only its most significant bit. -- The port attribute ``abc9_arrival`` specifies an integer (for output ports - only) to be used as the arrival time of this sequential port. It can be used, - for example, to specify the clk-to-Q delay of a flip-flop for consideration - during `abc9` techmapping. +- The output port attribute ``abc9_arrival`` specifies an integer, or a string + of space-separated integers to be used as the arrival time of this blackbox + port. It can be used, for example, to specify the clk-to-Q delay of a flip- + flop output for consideration during `abc9` techmapping. + +- The input port attribute ``abc9_requiredl`` specifies an integer, or a string + of space-separated integers to be used as the required time of this blackbox + port. It can be used, for example, to specify the setup-time of a flip-flop + input for consideration during `abc9` techmapping. - The module attribute ``abc9_flop`` is a boolean marking the module as a flip-flop. This allows `abc9` to analyse its contents in order to perform |