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author | Claire Wolf <claire@symbioticeda.com> | 2020-04-27 17:04:47 +0200 |
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committer | Claire Wolf <claire@symbioticeda.com> | 2020-05-02 11:21:01 +0200 |
commit | bbbce0d1c58f8bfb0a615f1ed53fa046552b5adf (patch) | |
tree | 6a8df40ad6343d3af573020f4e39e5a55f4da55a /README.md | |
parent | ca3fc3c882b9a454c48bee7d701fa5cb254ae671 (diff) | |
download | yosys-bbbce0d1c58f8bfb0a615f1ed53fa046552b5adf.tar.gz yosys-bbbce0d1c58f8bfb0a615f1ed53fa046552b5adf.tar.bz2 yosys-bbbce0d1c58f8bfb0a615f1ed53fa046552b5adf.zip |
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -281,6 +281,9 @@ Verilog Attributes and non-standard features temporary variable within an always block. This is mostly used internally by Yosys to synthesize Verilog functions and access arrays. +- The ``nowrshmsk`` attribute on a register prohibits the generation of + shift-and-mask type circuits for writing to bit slices of that register. + - The ``onehot`` attribute on wires mark them as one-hot state register. This is used for example for memory port sharing and set by the fsm_map pass. |