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| author | David Shah <dave@ds0.me> | 2019-11-22 15:32:46 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-02-02 16:13:13 +0000 |
| commit | 0488492ad269df9641ab317eac5568353dd61076 (patch) | |
| tree | 23d26103ac47ed62f2d0f805b6677943ef4f1795 /README.md | |
| parent | 4bfd2ef4f328b4a95918ed3e0d7a7e38406c4ae8 (diff) | |
| download | yosys-0488492ad269df9641ab317eac5568353dd61076.tar.gz yosys-0488492ad269df9641ab317eac5568353dd61076.tar.bz2 yosys-0488492ad269df9641ab317eac5568353dd61076.zip | |
Update CHANGELOG and README
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -387,6 +387,10 @@ Verilog Attributes and non-standard features according to the type of the always. These are checked for correctness in ``proc_dlatch``. +- The cell attribute ``wildcard_port_conns`` represents wildcard port + connections (SystemVerilog ``.*``). These are resolved to concrete + connections to matching wires in ``hierarchy``. + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset |