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| author | David Shah <dave@ds0.me> | 2019-09-20 13:01:47 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-10-03 09:54:45 +0100 |
| commit | 1746b6373b55490314bc2e12c6584c4a1cb38a6a (patch) | |
| tree | 079f006aacca52c45e9ccf4faaf1a7cc18427a15 /README.md | |
| parent | abc155715dbe8db5ee95707f7c243f23954ca139 (diff) | |
| download | yosys-1746b6373b55490314bc2e12c6584c4a1cb38a6a.tar.gz yosys-1746b6373b55490314bc2e12c6584c4a1cb38a6a.tar.bz2 yosys-1746b6373b55490314bc2e12c6584c4a1cb38a6a.zip | |
Update CHANGELOG and README
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -510,6 +510,8 @@ from SystemVerilog: into a design with ``read_verilog``, all its packages are available to SystemVerilog files being read into the same design afterwards. +- typedefs are supported (including inside packages) + - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether ports are inputs or outputs are supported. |