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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-19 11:37:11 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-06-19 11:37:11 +0200 |
| commit | 8d0cd529c936b1c0a38d7a71a4457bd84c8b3efe (patch) | |
| tree | 2e96384586fd4ede8e1b5d530a39e245cdc44370 /README.md | |
| parent | 6d64e242ba8214f7bceb35f688b544f56d49cea1 (diff) | |
| download | yosys-8d0cd529c936b1c0a38d7a71a4457bd84c8b3efe.tar.gz yosys-8d0cd529c936b1c0a38d7a71a4457bd84c8b3efe.tar.bz2 yosys-8d0cd529c936b1c0a38d7a71a4457bd84c8b3efe.zip | |
Add defaultvalue attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -350,6 +350,10 @@ Verilog Attributes and non-standard features through the synthesis. When entities are combined, a new |-separated string is created that contains all the string from the original entities. +- The ``defaultvalue`` attribute is used to store default values for + module inputs. The attribute is attached to the input wire by the HDL + front-end when the input is declared with a default value. + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset |