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* Remove trailing spaceEddie Hung2019-08-301-2/+2
* Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-281-15/+78
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| * Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
| * xilinx: Add SRLC16E primitive.Marcin Kościelnicki2019-08-271-1/+21
| * Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
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| * \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-11/+22
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| * \ \ Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-14/+20
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| * | | | move attributes to wiresMarcin Kościelnicki2019-08-131-33/+42
| * | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-131-0/+16
* | | | | Put attributes above portEddie Hung2019-08-231-19/+46
* | | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-231-5/+10
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| * | | | Forgot oneEddie Hung2019-08-231-1/+2
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| * | | Put abc_* attributes above portEddie Hung2019-08-231-7/+14
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* | | Add abc_arrival to SRL*Eddie Hung2019-08-211-3/+5
* | | OopsEddie Hung2019-08-201-1/+1
* | | xilinx to use abc_map.v with -max_iter 1Eddie Hung2019-08-201-3/+6
* | | Add reference to FD* timingEddie Hung2019-08-201-0/+2
* | | Remove sequential extensionEddie Hung2019-08-201-8/+16
* | | Remove SRL* delays from cells_sim.vEddie Hung2019-08-201-5/+3
* | | Wrap LUTRAMs in order to capture comb/seq behaviourEddie Hung2019-08-201-15/+9
* | | Add LUTRAM delaysEddie Hung2019-08-201-3/+6
* | | Use abc_{map,unmap,model}.vEddie Hung2019-08-201-8/+0
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-201-2/+2
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| * | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
* | | Add arrival times for SRL outputsEddie Hung2019-08-191-3/+5
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* / Attach abc_scc_break, abc_carry_{in,out} attr to ports not modulesEddie Hung2019-08-161-8/+20
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* xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...Marcin Kościelnicki2019-07-111-2/+2
* Revert "Fix broken MUXFx box, use MUXF7x2 box instead"Eddie Hung2019-07-011-3/+3
* Fix broken MUXFx box, use MUXF7x2 box insteadEddie Hung2019-07-011-3/+3
* Fix CARRY4 abc_box_idEddie Hung2019-06-281-1/+1
* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-281-2/+2
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| * Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-2/+2
| * Merge origin/masterEddie Hung2019-06-271-1/+1
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-261-3/+3
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| * Add "WE" to dist RAM's abc_scc_breakEddie Hung2019-06-261-3/+3
| * Add RAM32X1D box infoEddie Hung2019-06-251-2/+3
| * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-251-0/+17
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* | \ Merge remote-tracking branch 'origin/eddie/fix1132' into xc7muxEddie Hung2019-06-261-1/+1
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| * | | Simulation model verilog fixMiodrag Milanovic2019-06-261-1/+1
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* | | Cleanup abc_box_idEddie Hung2019-06-261-5/+5
* | | Add RAM32X1D box infoEddie Hung2019-06-241-2/+3
* | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-241-0/+2
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| * | Add Xilinx dist RAM as comb boxesEddie Hung2019-06-241-0/+2
* | | Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7muxEddie Hung2019-06-241-0/+17
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| * | Add RAM32X1D supportEddie Hung2019-06-241-0/+17
* | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-221-2/+0
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| * | Remove DFF and RAMD box info for nowEddie Hung2019-06-211-2/+0
* | | Add $__XILINX_MUXF78 to preserve entire boxEddie Hung2019-06-211-0/+8
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* | Remove WIP ABC9 flop supportEddie Hung2019-06-141-10/+10
* | Disable dist RAM boxes due to comb loopEddie Hung2019-06-111-2/+2