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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 20:07:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 20:07:38 -0700 |
| commit | 64d62710de4f1db0d59d7fa04b3fb4d51c8dff2e (patch) | |
| tree | 4fd972a04c38dc1013bb0ae16890cb89b691eb6a /techlibs/xilinx/cells_sim.v | |
| parent | affe9c9c1ad2dd208507931f0606c23941660d6b (diff) | |
| download | yosys-64d62710de4f1db0d59d7fa04b3fb4d51c8dff2e.tar.gz yosys-64d62710de4f1db0d59d7fa04b3fb4d51c8dff2e.tar.bz2 yosys-64d62710de4f1db0d59d7fa04b3fb4d51c8dff2e.zip | |
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Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3a58f32fa..80211619b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -299,7 +299,7 @@ endmodule module RAM32X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=11530 *) output DPO, SPO, + (* abc_arrival=1153 *) output DPO, SPO, input D, input WCLK, input WE, |