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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 09:56:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 09:56:17 -0700 |
| commit | d81a090d89d87837d3e18f9c724fe5c89ddf1f64 (patch) | |
| tree | 414787e8cdd565eaf225c3b0a21c56d8d4134697 /techlibs/xilinx/cells_sim.v | |
| parent | 5abe133323b2a6a46959f796c4730b2d70cdea26 (diff) | |
| download | yosys-d81a090d89d87837d3e18f9c724fe5c89ddf1f64.tar.gz yosys-d81a090d89d87837d3e18f9c724fe5c89ddf1f64.tar.bz2 yosys-d81a090d89d87837d3e18f9c724fe5c89ddf1f64.zip | |
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 910d0e246..bec9ea1a0 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -183,9 +183,9 @@ endmodule (* abc_box_id = 4, lib_whitebox *) module CARRY4( - (* abc_carry_out *) output [3:0] CO, + (* abc_carry *) output [3:0] CO, output [3:0] O, - (* abc_carry_in *) input CI, + (* abc_carry *) input CI, input CYINIT, input [3:0] DI, S ); |