diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 20:07:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 20:07:31 -0700 |
| commit | dbb8c8caaa50d83c12665b7cfd11d79e8af06196 (patch) | |
| tree | 4422b6cb7f3c8560847ead3545ea98b3638404eb /techlibs/xilinx/cells_sim.v | |
| parent | b9ff0503f39795a1f749c955b129d9972fe03f0a (diff) | |
| parent | c226af3f56957cc69b2ce8bb68a8259e26121ddc (diff) | |
| download | yosys-dbb8c8caaa50d83c12665b7cfd11d79e8af06196.tar.gz yosys-dbb8c8caaa50d83c12665b7cfd11d79e8af06196.tar.bz2 yosys-dbb8c8caaa50d83c12665b7cfd11d79e8af06196.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 354e4edbf..4a1e334d6 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -289,7 +289,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 5, abc_scc_break="D" *) +(* abc_box_id = 5, abc_scc_break="D,WE" *) module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, @@ -307,7 +307,7 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 6, abc_scc_break="D" *) +(* abc_box_id = 6, abc_scc_break="D,WE" *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -325,7 +325,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 7, abc_scc_break="D" *) +(* abc_box_id = 7, abc_scc_break="D,WE" *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |