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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-08-27 18:08:51 +0200 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-08-27 20:27:12 +0200 |
| commit | d361f5ab795f5b823a594f1fee75f93a78995481 (patch) | |
| tree | 61354ed5a04a9b6a79fa737be376e1dfd3212b35 /techlibs/xilinx/cells_sim.v | |
| parent | eab3c1432b717bb341773878bf0daece7d39dec8 (diff) | |
| download | yosys-d361f5ab795f5b823a594f1fee75f93a78995481.tar.gz yosys-d361f5ab795f5b823a594f1fee75f93a78995481.tar.bz2 yosys-d361f5ab795f5b823a594f1fee75f93a78995481.zip | |
xilinx: Add SRLC16E primitive.
Fixes #1331.
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index aeef7f885..973e17212 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -394,7 +394,27 @@ module SRL16E ( always @(negedge CLK) if (CE) r <= { r[14:0], D }; end else - always @(posedge CLK) if (CE) r <= { r[14:0], D }; + always @(posedge CLK) if (CE) r <= { r[14:0], D }; + endgenerate +endmodule + +module SRLC16E ( + output Q, + output Q15, + input A0, A1, A2, A3, CE, CLK, D +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + + reg [15:0] r = INIT; + assign Q15 = r[15]; + assign Q = r[{A3,A2,A1,A0}]; + generate + if (IS_CLK_INVERTED) begin + always @(negedge CLK) if (CE) r <= { r[14:0], D }; + end + else + always @(posedge CLK) if (CE) r <= { r[14:0], D }; endgenerate endmodule |