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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 10:51:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 10:51:39 -0700 |
| commit | 9314a0a42ec05e82d2d3d77aebddfb06271a4730 (patch) | |
| tree | 9251ba658029484731a53e68bd8e14d2c5f8a3e8 /techlibs/xilinx/cells_sim.v | |
| parent | 13424352cc8dca5f08ad22aa42066dc7f62afea5 (diff) | |
| download | yosys-9314a0a42ec05e82d2d3d77aebddfb06271a4730.tar.gz yosys-9314a0a42ec05e82d2d3d77aebddfb06271a4730.tar.bz2 yosys-9314a0a42ec05e82d2d3d77aebddfb06271a4730.zip | |
Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 973e17212..e12b77c02 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -380,9 +380,10 @@ endmodule module SRL16E ( output Q, + input A0, A1, A2, A3, CE, (* clkbuf_sink *) input CLK, - input A0, A1, A2, A3, CE, D + input D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -401,7 +402,10 @@ endmodule module SRLC16E ( output Q, output Q15, - input A0, A1, A2, A3, CE, CLK, D + input A0, A1, A2, A3, CE, + (* clkbuf_sink *) + input CLK, + input D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -422,9 +426,10 @@ module SRLC32E ( output Q, output Q31, input [4:0] A, + input CE, (* clkbuf_sink *) input CLK, - input CE, D + input D ); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_CLK_INVERTED = 1'b0; |