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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 14:48:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 14:48:35 -0700 |
| commit | 812469aaa351792a5215ed871de59b544934f5e5 (patch) | |
| tree | 4b03037dcf606b19f908e3ec6fce616fe13a2eee /techlibs/xilinx/cells_sim.v | |
| parent | c762be593042ed5d812a3a37d494a82565cbaad0 (diff) | |
| parent | b2b5cf78e21def63c54c080217d77afefba8e4c7 (diff) | |
| download | yosys-812469aaa351792a5215ed871de59b544934f5e5.tar.gz yosys-812469aaa351792a5215ed871de59b544934f5e5.tar.bz2 yosys-812469aaa351792a5215ed871de59b544934f5e5.zip | |
Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 58e9c74d5..354e4edbf 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -294,7 +294,7 @@ module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, input A0, A1, A2, A3, A4, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); parameter INIT = 32'h0; parameter IS_WCLK_INVERTED = 1'b0; |