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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 14:01:09 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 14:01:09 -0700 |
| commit | 09ac27471667d1316b09984624dde981e860a94e (patch) | |
| tree | 214139925e9a3c61e2384857ed28f8689e6f8507 /techlibs/xilinx/cells_sim.v | |
| parent | a9a140aa6c84e71edc1a244cfe363400c7e09d90 (diff) | |
| download | yosys-09ac27471667d1316b09984624dde981e860a94e.tar.gz yosys-09ac27471667d1316b09984624dde981e860a94e.tar.bz2 yosys-09ac27471667d1316b09984624dde981e860a94e.zip | |
Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
This reverts commit a9a140aa6c84e71edc1a244cfe363400c7e09d90.
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d1877cf1a..3937d3536 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -171,9 +171,9 @@ endmodule `ifdef _ABC (* abc_box_id = 3, lib_whitebox *) -module \$__XILINX_MUXF7x2 (output O0, O1, input I0, I1, I2, I3, S); - assign O0 = S ? I1 : I0; - assign O1 = S ? I3 : I2; +module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); + assign O = S1 ? (S0 ? I3 : I2) + : (S0 ? I1 : I0); endmodule `endif |