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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:23:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:23:50 -0700 |
| commit | 509c353fe981c95ca667a637bf2b47477962a60b (patch) | |
| tree | 4c5511d35ba36745bf3d645d1690fc1fbe3de512 /techlibs/xilinx/cells_sim.v | |
| parent | a270af00cc133ac03ec97cf81ed0a7146b7b225e (diff) | |
| download | yosys-509c353fe981c95ca667a637bf2b47477962a60b.tar.gz yosys-509c353fe981c95ca667a637bf2b47477962a60b.tar.bz2 yosys-509c353fe981c95ca667a637bf2b47477962a60b.zip | |
Forgot one
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index e3897d9a6..3ad96d7fb 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -325,7 +325,8 @@ module RAM64X1D ( (* abc_scc_break *) input D, input WCLK, - (* abc_scc_break *) input WE, + (* abc_scc_break *) + input WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 ); |