diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 20:41:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 20:41:14 -0700 |
| commit | 65c022c2572036a66bd06bafd3e3efa088aafb79 (patch) | |
| tree | 3f246df4467b08caf9c0d2954974560e8af5f3b5 /techlibs/xilinx/cells_sim.v | |
| parent | 8d18c256f0d6fee25fe7a55ed7d882c478465b09 (diff) | |
| download | yosys-65c022c2572036a66bd06bafd3e3efa088aafb79.tar.gz yosys-65c022c2572036a66bd06bafd3e3efa088aafb79.tar.bz2 yosys-65c022c2572036a66bd06bafd3e3efa088aafb79.zip | |
Remove DFF and RAMD box info for now
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index bf7a0ed44..84939818e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,7 +281,6 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -//(* abc_box_id = 4 /*, lib_whitebox*/ *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -299,7 +298,6 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -//(* abc_box_id = 5 /*, lib_whitebox*/ *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |