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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:48:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:48:49 -0700 |
| commit | 1564eb8b549a0927efa4d2b4cbc479038993024a (patch) | |
| tree | b31c219fd98a8d0c8bb4542c10f5961529bd9635 /techlibs/xilinx/cells_sim.v | |
| parent | f1675b88f63b4c279e368d5ec9e6ca48f528024d (diff) | |
| parent | a19226c174e31da444b831706adf7fa17e9cb9e4 (diff) | |
| download | yosys-1564eb8b549a0927efa4d2b4cbc479038993024a.tar.gz yosys-1564eb8b549a0927efa4d2b4cbc479038993024a.tar.bz2 yosys-1564eb8b549a0927efa4d2b4cbc479038993024a.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 29abc9807..c6c49c3cd 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -306,6 +306,7 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule +(* abc_box_id = 4, abc_scc_break="D" *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -323,6 +324,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule +(* abc_box_id = 5, abc_scc_break="D" *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |