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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-07-11 21:13:12 +0200 |
|---|---|---|
| committer | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-07-11 21:13:12 +0200 |
| commit | a9efacd01da0feb85000ce62c2769c35eae43505 (patch) | |
| tree | f9fe236a929a1bfe5ad3343e7056365589962d2d /techlibs/xilinx/cells_sim.v | |
| parent | 9112850800a92ed0e330d8470e1273116d78ba14 (diff) | |
| download | yosys-a9efacd01da0feb85000ce62c2769c35eae43505.tar.gz yosys-a9efacd01da0feb85000ce62c2769c35eae43505.tar.bz2 yosys-a9efacd01da0feb85000ce62c2769c35eae43505.zip | |
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3937d3536..05e46b4e7 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -226,7 +226,7 @@ module FDRE (output reg Q, input C, CE, D, R); endmodule module FDSE (output reg Q, input C, CE, D, S); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; @@ -252,7 +252,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); endmodule module FDPE (output reg Q, input C, CE, D, PRE); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; |