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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 16:44:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 16:44:11 -0700 |
| commit | f33abd4eab08c0557a561b0fd4f16fc3d86433ab (patch) | |
| tree | 3839e0b5d7f7fb5ec3cab921e0e363f43f42a1f7 /techlibs/xilinx/cells_sim.v | |
| parent | c7f1ccbcb0b36093f619bbbd3c5dd621161134de (diff) | |
| download | yosys-f33abd4eab08c0557a561b0fd4f16fc3d86433ab.tar.gz yosys-f33abd4eab08c0557a561b0fd4f16fc3d86433ab.tar.bz2 yosys-f33abd4eab08c0557a561b0fd4f16fc3d86433ab.zip | |
Remove trailing space
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index b4657daca..6e8729256 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -269,7 +269,7 @@ endmodule module FDCE ( (* abc_arrival=303 *) output reg Q, - (* clkbuf_sink *) + (* clkbuf_sink *) input C, input CE, D, CLR ); @@ -289,7 +289,7 @@ endmodule module FDPE ( (* abc_arrival=303 *) output reg Q, - (* clkbuf_sink *) + (* clkbuf_sink *) input C, input CE, D, PRE ); |