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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 19:47:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 19:47:11 -0700 |
| commit | c26c5563845d81048dea35c4aef5f4678e177b23 (patch) | |
| tree | 966210f9e81cad2fd9180a9123e073bd55a17521 /techlibs/xilinx/cells_sim.v | |
| parent | 6b1b03d9f771addbd54358299faad181b589c9f8 (diff) | |
| download | yosys-c26c5563845d81048dea35c4aef5f4678e177b23.tar.gz yosys-c26c5563845d81048dea35c4aef5f4678e177b23.tar.bz2 yosys-c26c5563845d81048dea35c4aef5f4678e177b23.zip | |
xilinx to use abc_map.v with -max_iter 1
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 6aba5a4b2..3a58f32fa 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -298,7 +298,8 @@ module FDPE_1 ((* abc_arrival=303 *) output reg Q, endmodule module RAM32X1D ( - output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc_arrival=11530 *) output DPO, SPO, input D, input WCLK, input WE, @@ -317,7 +318,8 @@ module RAM32X1D ( endmodule module RAM64X1D ( - output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc_arrival=1153 *) output DPO, SPO, input D, input WCLK, input WE, @@ -336,7 +338,8 @@ module RAM64X1D ( endmodule module RAM128X1D ( - output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc_arrival=1153 *) output DPO, SPO, input D, input WCLK, input WE, |