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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 12:02:51 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 12:02:51 -0700 |
| commit | 54379f9872ba3abdf5328994abcf5abfc7288c6b (patch) | |
| tree | 6213f8f04492f2868737a4a8348abfd07e0f7c80 /techlibs/xilinx/cells_sim.v | |
| parent | 8a708d1fdb662f86a46720200fa15acafde30333 (diff) | |
| download | yosys-54379f9872ba3abdf5328994abcf5abfc7288c6b.tar.gz yosys-54379f9872ba3abdf5328994abcf5abfc7288c6b.tar.bz2 yosys-54379f9872ba3abdf5328994abcf5abfc7288c6b.zip | |
Disable dist RAM boxes due to comb loop
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 14e35737e..d9aa36666 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 4 /*, lib_whitebox*/ *) +//(* abc_box_id = 4 /*, lib_whitebox*/ *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -299,7 +299,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 5 /*, lib_whitebox*/ *) +//(* abc_box_id = 5 /*, lib_whitebox*/ *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |