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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:33:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:33:11 -0700 |
| commit | 6f36ec8ecf147f8d669f35dd616714af971db6f4 (patch) | |
| tree | 04dc0222fd51dd70edef52b733cecd2a9179c093 /techlibs/xilinx/cells_sim.v | |
| parent | d2fed0a7f1bb72ee285657b974f4996c77641a23 (diff) | |
| parent | ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7 (diff) | |
| download | yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.tar.gz yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.tar.bz2 yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 8261286af..67b221c95 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,6 +281,23 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +module RAM32X1D ( + output DPO, SPO, + input D, WCLK, WE, + input A0, A1, A2, A3, A4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, +); + parameter INIT = 32'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [31:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + (* abc_box_id = 4, abc_scc_break="D" *) module RAM64X1D ( output DPO, SPO, |