| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Update README to use "read" instead of "read_verilog" | Clifford Wolf | 2019-07-29 | 1 | -48/+19 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add support for reading gzip'd input files | David Shah | 2019-07-26 | 1 | -3/+3 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Updated FreeBSD dependencies in README.md | Roman-Parise | 2019-07-14 | 1 | -1/+1 |
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| * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 1 | -0/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 1 | -0/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | README.md: Missing formatting for <tag> | Tux3 | 2019-06-04 | 1 | -1/+1 |
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| * | Refactor hierarchy wand/wor handling | Clifford Wolf | 2019-05-28 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | update README.md with wand/wor information | Stefan Biereigel | 2019-05-27 | 1 | -2/+2 |
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| * | Add $stop to documentation | Clifford Wolf | 2019-05-09 | 1 | -3/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Update README | Clifford Wolf | 2019-05-04 | 1 | -5/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add specify support to README | Clifford Wolf | 2019-04-23 | 1 | -0/+5 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Format some names using inline code | Eddie Hung | 2019-04-23 | 1 | -2/+2 |
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| * | Fix spelling | Eddie Hung | 2019-04-23 | 1 | -1/+1 |
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| * | Merge pull request #905 from christian-krieg/feature/python_bindings | Clifford Wolf | 2019-04-22 | 1 | -4/+5 |
| |\ | | | | | Feature/python bindings | ||||
| | * | Changed filesystem dependency to boost instead of experimental std library | Benedikt Tutzer | 2019-04-04 | 1 | -1/+1 |
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| | * | Added dependencies to README and travis configuration | Benedikt Tutzer | 2019-04-03 | 1 | -4/+5 |
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| * | | Add "noblackbox" attribute | Clifford Wolf | 2019-04-21 | 1 | -1/+6 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -0/+3 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -0/+4 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | README: fix some incorrect quoting. | whitequark | 2019-04-15 | 1 | -2/+2 |
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| * | Add "hdlname" attribute | Clifford Wolf | 2019-03-26 | 1 | -0/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add note about test requirements in README | Felix Vietmeyer | 2019-03-16 | 1 | -1/+4 |
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| * | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 1 | -0/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Minor improvements in README | Clifford Wolf | 2019-03-01 | 1 | -3/+16 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -9/+9 |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | ||||
| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 1 | -0/+3 |
| |\ | | | | | Support for SystemVerilog interfaces and modports | ||||
| | * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -0/+3 |
| | | | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) | ||||
| * | | We have 2018 now | Clifford Wolf | 2018-10-16 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix Cygwin build and document needed packages | Miodrag Milanovic | 2018-09-19 | 1 | -0/+4 |
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| * | readme: Fix formatting of a keyword | Konrad Beckmann | 2018-08-06 | 1 | -1/+1 |
| | | | | | | Single quotes were used instead of backticks leading to incorrect formatting. | ||||
| * | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 1 | -1/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Remove mercurial from build instructions | Clifford Wolf | 2018-05-15 | 1 | -3/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | update README | Johnny Sorocil | 2018-05-06 | 1 | -0/+8 |
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| * | Add documentation for anyconst/anyseq/allconst/allseq attribute | Clifford Wolf | 2018-04-06 | 1 | -0/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Small fixes and improvements in $allconst/$allseq handling | Clifford Wolf | 2018-02-26 | 1 | -4/+5 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -2/+7 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Adding COPYING file with license information. | Tim 'mithro' Ansell | 2017-10-19 | 1 | -1/+1 |
| | | | | | | This allows GitHub and other tools to detect the license info. Providing a COPYING for LICENSE file is also pretty standard. | ||||
| * | delete bad backslash | Stephen | 2017-09-27 | 1 | -1/+1 |
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| * | Add osx tests using brew bundle | Stephen Groat | 2017-09-27 | 1 | -2/+1 |
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| * | Merge branch 'master' of https://github.com/stv0g/yosys into stv0g-master | Clifford Wolf | 2017-02-11 | 1 | -3/+13 |
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| | * | Remove space after backslash | Steffen Vogel | 2017-02-09 | 1 | -1/+1 |
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| | * | Applied fixes from @joshhead (thanks for your effors!) | Steffen Vogel | 2017-02-09 | 1 | -1/+1 |
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| | * | Added notes for compilation on OS X | Steffen Vogel | 2017-02-07 | 1 | -3/+13 |
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| * | | Add checker support to verilog front-end | Clifford Wolf | 2017-02-09 | 1 | -3/+9 |
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| * | | Add SV "rand" and "const rand" support | Clifford Wolf | 2017-02-08 | 1 | -2/+5 |
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| * | | Further improve cover() support | Clifford Wolf | 2017-02-04 | 1 | -5/+5 |
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| * | Keep lines under 80 characters | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-19 | 1 | -10/+11 |
| | | | | | | Recent README changes added some characters to existing lines, which made them longer than 80 characters. This commit fixes that. | ||||
| * | Markdownify README even further | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-19 | 1 | -60/+60 |
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| * | Markdownify README | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-12 | 1 | -0/+444 |
| This is the first commit in series. There are many other things that could be improved, this is just the first renderable version. | |||||
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index : iCE40/yosys | |
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