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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-23 23:01:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 23:01:38 +0200 |
| commit | 67005633e246e47683b11e13f08afb788bc9de02 (patch) | |
| tree | d290e43efc572083c5fbe310e1262fb56b39bf3b /README.md | |
| parent | 64925b4e8f7890f5447d9655b2c69dd59a93f7cd (diff) | |
| download | yosys-67005633e246e47683b11e13f08afb788bc9de02.tar.gz yosys-67005633e246e47683b11e13f08afb788bc9de02.tar.bz2 yosys-67005633e246e47683b11e13f08afb788bc9de02.zip | |
Add specify support to README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -424,6 +424,11 @@ Verilog Attributes and non-standard features in an unconditional context (only if/case statements on parameters and constant values). The intended use for this is synthesis-time DRC. +- There is limited support for converting specify .. endspecify statements to + special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in + blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this + functionality. (By default specify .. endspecify blocks are ignored.) + Non-standard or SystemVerilog features for formal verification ============================================================== |