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| author | Clifford Wolf <clifford@clifford.at> | 2018-04-06 14:37:43 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-04-06 14:37:43 +0200 |
| commit | 035f778121c179e0712e6c81f19195d0ab2c2f35 (patch) | |
| tree | fa708f254ff53d675887462b934f84f53ac03428 /README.md | |
| parent | 5ea2c53604aefeeaf43a638fe3c86813e947dc37 (diff) | |
| download | yosys-035f778121c179e0712e6c81f19195d0ab2c2f35.tar.gz yosys-035f778121c179e0712e6c81f19195d0ab2c2f35.tar.bz2 yosys-035f778121c179e0712e6c81f19195d0ab2c2f35.zip | |
Add documentation for anyconst/anyseq/allconst/allseq attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -402,6 +402,10 @@ Non-standard or SystemVerilog features for formal verification statements it is sufficient if just one ``$allconst/$allseq`` value triggers the property (similar to ``$anyconst/$anyseq``). +- Wires/registers decalred using the ``anyconst/anyseq/allconst/allseq`` attribute + (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven + by a ``$anyconst/$anyseq/$allconst/$allseq`` function. + - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are supported in any clocked block. |