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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-18 10:58:47 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-18 10:58:47 +0200 |
| commit | f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c (patch) | |
| tree | 1778829a6932d18730a3a085a80a65205189c7ba /README.md | |
| parent | 24a5c6585678f89058382fe2c3f36b821b419e90 (diff) | |
| parent | 736105b0468f9468f00915cad60949535ce5a496 (diff) | |
| download | yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.gz yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.bz2 yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.zip | |
Merge pull request #659 from rubund/sv_interfaces
Support for SystemVerilog interfaces and modports
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -452,6 +452,9 @@ from SystemVerilog: into a design with ``read_verilog``, all its packages are available to SystemVerilog files being read into the same design afterwards. +- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether + ports are inputs or outputs are supported. + Building the documentation ========================== |