diff options
| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-13 20:34:44 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-13 20:34:44 +0200 |
| commit | c50afc4246d552db079aec303b0d79ae92107a67 (patch) | |
| tree | 546271de9e8e4f61697785d0687ab289152ac6ca /README.md | |
| parent | a36d1701dd99736b82f64ed870e7464f2deae220 (diff) | |
| download | yosys-c50afc4246d552db079aec303b0d79ae92107a67.tar.gz yosys-c50afc4246d552db079aec303b0d79ae92107a67.tar.bz2 yosys-c50afc4246d552db079aec303b0d79ae92107a67.zip | |
Documentation improvements etc.
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -452,6 +452,9 @@ from SystemVerilog: into a design with ``read_verilog``, all its packages are available to SystemVerilog files being read into the same design afterwards. +- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether + ports are inputs or outputs are supported. + Building the documentation ========================== |