Fix typographical and grammatical errors and inconsistencies.

The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.

1 files changed, 9 insertions, 9 deletions

diff --git a/README.md b/README.md
index 840f2c8b2..883f2b0a5 100644
--- a/README.md
+++ b/README.md
@@ -117,7 +117,7 @@ reading the design using the Verilog frontend:
 
 	yosys> read_verilog tests/simple/fiedler-cooley.v
 
-writing the design to the console in yosys's internal format:
+writing the design to the console in Yosys's internal format:
 
 	yosys> write_ilang
 
@@ -234,7 +234,7 @@ Unsupported Verilog-2005 Features
 =================================
 
 The following Verilog-2005 features are not supported by
-yosys and there are currently no plans to add support
+Yosys and there are currently no plans to add support
 for them:
 
 - Non-synthesizable language features as defined in
@@ -285,9 +285,9 @@ Verilog Attributes and non-standard features
   storage element. The register itself will always have all bits set
   to 'x' (undefined). The variable may only be used as blocking assigned
   temporary variable within an always block. This is mostly used internally
-  by yosys to synthesize Verilog functions and access arrays.
+  by Yosys to synthesize Verilog functions and access arrays.
 
-- The ``onehot`` attribute on wires mark them as onehot state register. This
+- The ``onehot`` attribute on wires mark them as one-hot state register. This
   is used for example for memory port sharing and set by the fsm_map pass.
 
 - The ``blackbox`` attribute on modules is used to mark empty stub modules
@@ -319,13 +319,13 @@ Verilog Attributes and non-standard features
   through the synthesis. When entities are combined, a new |-separated
   string is created that contains all the string from the original entities.
 
-- In addition to the ``(* ... *)`` attribute syntax, yosys supports
+- In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset
   by adding an empty ``{* *}`` statement.)
 
 - In module parameter and port declarations, and cell port and parameter
-  lists, a trailing comma is ignored. This simplifies writing verilog code
+  lists, a trailing comma is ignored. This simplifies writing Verilog code
   generators a bit in some cases.
 
 - Modules can be declared with ``module mod_name(...);`` (with three dots
@@ -410,11 +410,11 @@ Non-standard or SystemVerilog features for formal verification
 
 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
   formal exist-forall problems. Assumptions only hold if the trace satisfies
-  the assumtion for all ``$allconst/$allseq`` values. For assertions and cover
+  the assumption for all ``$allconst/$allseq`` values. For assertions and cover
   statements it is sufficient if just one ``$allconst/$allseq`` value triggers
   the property (similar to ``$anyconst/$anyseq``).
 
-- Wires/registers decalred using the ``anyconst/anyseq/allconst/allseq`` attribute
+- Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute
   (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
   by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
 
@@ -485,6 +485,6 @@ Then execute, from the root of the repository:
 
 Notes:
 
-- To run `make manual` you need to have installed yosys with `make install`,
+- To run `make manual` you need to have installed Yosys with `make install`,
   otherwise it will fail on finding `kernel/yosys.h` while building
   `PRESENTATION_Prog`.