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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-08 14:38:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-08 14:38:15 +0100 |
| commit | ef4a28e112be10d3d62395f68e53e8b7e42dbf68 (patch) | |
| tree | c993cbb2d319288c7561c12264babda628a38b3d /README.md | |
| parent | 1d1f56a3617dcee6d856a29d1d8576969bf8dce5 (diff) | |
| download | yosys-ef4a28e112be10d3d62395f68e53e8b7e42dbf68.tar.gz yosys-ef4a28e112be10d3d62395f68e53e8b7e42dbf68.tar.bz2 yosys-ef4a28e112be10d3d62395f68e53e8b7e42dbf68.zip | |
Add SV "rand" and "const rand" support
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 7 |
1 files changed, 5 insertions, 2 deletions
@@ -378,10 +378,11 @@ Non-standard or SystemVerilog features for formal verification - The system task ``$initstate`` evaluates to 1 in the initial state and to 0 otherwise. -- The system task ``$anyconst`` evaluates to any constant value. +- The system task ``$anyconst`` evaluates to any constant value. This is + equivalent to declaring a reg as ``const rand``. - The system task ``$anyseq`` evaluates to any value, possibly a different - value in each cycle. + value in each cycle. This is equivalent to declaring a reg as ``rand``. - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are supported in any clocked block. @@ -406,6 +407,8 @@ from SystemVerilog: - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic`` and ``bit`` are supported. +- Declaring free variables with ``rand`` and ``const rand`` is supported. + - SystemVerilog packages are supported. Once a SystemVerilog file is read into a design with ``read_verilog``, all its packages are available to SystemVerilog files being read into the same design afterwards. |