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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-20 22:24:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-20 22:24:50 +0200 |
| commit | fb7f02be5561ccfd5bee5f3235fbbae5ef618f36 (patch) | |
| tree | 76e175ebc3419b6d0bc12cb2a6d5e557ac839af7 /README.md | |
| parent | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (diff) | |
| download | yosys-fb7f02be5561ccfd5bee5f3235fbbae5ef618f36.tar.gz yosys-fb7f02be5561ccfd5bee5f3235fbbae5ef618f36.tar.bz2 yosys-fb7f02be5561ccfd5bee5f3235fbbae5ef618f36.zip | |
New behavior for front-end handling of whiteboxes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -316,6 +316,9 @@ Verilog Attributes and non-standard features ``blackbox``, but is for whitebox modules, i.e. library modules that contain a behavioral model of the cell type. +- The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog`` + is run in `-lib` mode. Otherwise it's automatically removed. + - The ``dynports`` attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. |