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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-09 15:31:40 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-09 15:31:40 +0200 |
| commit | 05a5027db87cd4e5f88a24d0e4c5c9eb77225a5d (patch) | |
| tree | d3bcafccc3a4d3e2183c3896e502b7563492ae2f /README.md | |
| parent | caad497839d0d3aa91b02ce970968ad4e2c1ad88 (diff) | |
| download | yosys-05a5027db87cd4e5f88a24d0e4c5c9eb77225a5d.tar.gz yosys-05a5027db87cd4e5f88a24d0e4c5c9eb77225a5d.tar.bz2 yosys-05a5027db87cd4e5f88a24d0e4c5c9eb77225a5d.zip | |
Add $stop to documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 7 |
1 files changed, 4 insertions, 3 deletions
@@ -416,9 +416,10 @@ Verilog Attributes and non-standard features expressions as <size>. If the expression is not a simple identifier, it must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` -- The system tasks ``$finish`` and ``$display`` are supported in initial blocks - in an unconditional context (only if/case statements on parameters - and constant values). The intended use for this is synthesis-time DRC. +- The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in + initial blocks in an unconditional context (only if/case statements on + expressions over parameters and constant values are allowed). The intended + use for this is synthesis-time DRC. - There is limited support for converting specify .. endspecify statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in |