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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-26 14:51:35 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-26 14:52:48 +0100 |
| commit | d0b9b1bece9866fd7b0e153c991fc7e9b57a1efc (patch) | |
| tree | df8908d5062a5152a829d5a9c0b12a27923d5b4e /README.md | |
| parent | c863796e9ff91c76f0f8679b6871b8ffcb75edb6 (diff) | |
| download | yosys-d0b9b1bece9866fd7b0e153c991fc7e9b57a1efc.tar.gz yosys-d0b9b1bece9866fd7b0e153c991fc7e9b57a1efc.tar.bz2 yosys-d0b9b1bece9866fd7b0e153c991fc7e9b57a1efc.zip | |
Add "hdlname" attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -315,6 +315,9 @@ Verilog Attributes and non-standard features - The ``dynports'' attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. +- The ``hdlname'' attribute is used by some passes to document the original + (HDL) name of a module when renaming a module. + - The ``keep`` attribute on cells and wires is used to mark objects that should never be removed by the optimizer. This is used for example for cells that have hidden connections that are not part of the netlist, such as IO pads. |