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| author | Clifford Wolf <clifford@clifford.at> | 2018-06-01 13:25:42 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2018-06-01 13:25:42 +0200 |
| commit | 4372cf690d829755279a6a5778023e5e0a4493b2 (patch) | |
| tree | 1598748761fe015b7f95b4c3c89679f36ccd7f0a /README.md | |
| parent | f273291dfe5de460192ef2a63a121b3c2e8b9a62 (diff) | |
| download | yosys-4372cf690d829755279a6a5778023e5e0a4493b2.tar.gz yosys-4372cf690d829755279a6a5778023e5e0a4493b2.tar.bz2 yosys-4372cf690d829755279a6a5778023e5e0a4493b2.zip | |
Add (* gclk *) attribute support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -418,7 +418,9 @@ Non-standard or SystemVerilog features for formal verification supported in any clocked block. - The syntax ``@($global_clock)`` can be used to create FFs that have no - explicit clock input ($ff cells). + explicit clock input ($ff cells). The same can be achieved by using + ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>`` + is marked with the ``(* gclk *)`` Verilog attribute. Supported features from SystemVerilog |