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authorClifford Wolf <clifford@clifford.at>2018-02-26 11:58:44 +0100
committerClifford Wolf <clifford@clifford.at>2018-02-26 11:58:44 +0100
commit675dd5347ad7bafdfa95f97b60996595a32f2c7d (patch)
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parentfba499b8666ef33bc5b11ce2df7b8b18a5aeaa75 (diff)
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Small fixes and improvements in $allconst/$allseq handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@@ -396,10 +396,11 @@ Non-standard or SystemVerilog features for formal verification
but also works outside of checkers. (Yosys also supports ``rand``
variables outside checkers.)
-- The system functions ``$allconst`` and ``$allseq`` are used to construct formal
- exist-forall problems. Assertions are only violated if the trace vialoates
- the assertion for all ``$allconst/$allseq`` values and assumptions only hold
- if the trace satisfies the assumtion for all ``$allconst/$allseq`` values.
+- The system functions ``$allconst`` and ``$allseq`` can be used to construct
+ formal exist-forall problems. Assumptions only hold if the trace satisfies
+ the assumtion for all ``$allconst/$allseq`` values. For assertions and cover
+ statements it is sufficient if just one ``$allconst/$allseq`` value triggers
+ the property (similar to ``$anyconst/$anyseq``).
- The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
supported in any clocked block.