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| * Add doc for abc_* attributesEddie Hung2019-08-161-0/+16
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* | README updatesMarcin Koƛcielnicki2019-08-131-0/+14
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* Update README to use "read" instead of "read_verilog"Clifford Wolf2019-07-291-48/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for reading gzip'd input filesDavid Shah2019-07-261-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Updated FreeBSD dependencies in README.mdRoman-Parise2019-07-141-1/+1
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* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add defaultvalue attributeClifford Wolf2019-06-191-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* README.md: Missing formatting for <tag>Tux32019-06-041-1/+1
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* Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* update README.md with wand/wor informationStefan Biereigel2019-05-271-2/+2
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* Add $stop to documentationClifford Wolf2019-05-091-3/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update READMEClifford Wolf2019-05-041-5/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add specify support to READMEClifford Wolf2019-04-231-0/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Format some names using inline codeEddie Hung2019-04-231-2/+2
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* Fix spellingEddie Hung2019-04-231-1/+1
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* Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-221-4/+5
|\ | | | | Feature/python bindings
| * Changed filesystem dependency to boost instead of experimental std libraryBenedikt Tutzer2019-04-041-1/+1
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| * Added dependencies to README and travis configurationBenedikt Tutzer2019-04-031-4/+5
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* | Add "noblackbox" attributeClifford Wolf2019-04-211-1/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | New behavior for front-end handling of whiteboxesClifford Wolf2019-04-201-0/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-0/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | README: fix some incorrect quoting.whitequark2019-04-151-2/+2
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* Add "hdlname" attributeClifford Wolf2019-03-261-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add note about test requirements in READMEFelix Vietmeyer2019-03-161-1/+4
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* Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Minor improvements in READMEClifford Wolf2019-03-011-3/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-9/+9
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-181-0/+3
|\ | | | | Support for SystemVerilog interfaces and modports
| * Documentation improvements etc.Ruben Undheim2018-10-131-0/+3
| | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
* | We have 2018 nowClifford Wolf2018-10-161-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix Cygwin build and document needed packagesMiodrag Milanovic2018-09-191-0/+4
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* readme: Fix formatting of a keywordKonrad Beckmann2018-08-061-1/+1
| | | | | Single quotes were used instead of backticks leading to incorrect formatting.
* Add (* gclk *) attribute supportClifford Wolf2018-06-011-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove mercurial from build instructionsClifford Wolf2018-05-151-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* update READMEJohnny Sorocil2018-05-061-0/+8
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* Add documentation for anyconst/anyseq/allconst/allseq attributeClifford Wolf2018-04-061-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Small fixes and improvements in $allconst/$allseq handlingClifford Wolf2018-02-261-4/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-2/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Adding COPYING file with license information.Tim 'mithro' Ansell2017-10-191-1/+1
| | | | | This allows GitHub and other tools to detect the license info. Providing a COPYING for LICENSE file is also pretty standard.
* delete bad backslashStephen2017-09-271-1/+1
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* Add osx tests using brew bundleStephen Groat2017-09-271-2/+1
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* Merge branch 'master' of https://github.com/stv0g/yosys into stv0g-masterClifford Wolf2017-02-111-3/+13
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| * Remove space after backslashSteffen Vogel2017-02-091-1/+1
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| * Applied fixes from @joshhead (thanks for your effors!)Steffen Vogel2017-02-091-1/+1
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| * Added notes for compilation on OS XSteffen Vogel2017-02-071-3/+13
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* | Add checker support to verilog front-endClifford Wolf2017-02-091-3/+9
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* | Add SV "rand" and "const rand" supportClifford Wolf2017-02-081-2/+5
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* | Further improve cover() supportClifford Wolf2017-02-041-5/+5
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* Keep lines under 80 charactersAleks-Daniel Jakimenko-Aleksejev2016-11-191-10/+11
| | | | | Recent README changes added some characters to existing lines, which made them longer than 80 characters. This commit fixes that.
* Markdownify README even furtherAleks-Daniel Jakimenko-Aleksejev2016-11-191-60/+60
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