iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| * \| \| \| \| \| \| \| \|	xilinx: Add URAM288 mapping for xcup	David Shah	2019-10-23	5	-2/+92
\| * \| \| \| \| \| \| \| \|	xilinx: Add support for UltraScale[+] BRAM mapping	David Shah	2019-10-23	7	-416/+1062
* \| \| \| \| \| \| \| \| \|	Add "verific -L"	Clifford Wolf	2019-10-24	1	-1/+12
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* \| \| \| \| \| \| \| \|	Bugfix in smtio vcd handling of $-identifiers	Clifford Wolf	2019-10-23	1	-6/+9
* \| \| \| \| \| \| \| \|	xilinx: Support multiplier mapping for all families.	Marcin Kościelnicki	2019-10-22	9	-9/+269
* \| \| \| \| \| \| \| \|	Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg	Clifford Wolf	2019-10-22	2	-0/+2
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\| * \| \| \| \| \| \| \| \|	Call memory_dff before DSP mapping to reserve registers (fixes #1447)	N. Engelhardt	2019-10-17	2	-0/+2
* \| \| \| \| \| \| \| \| \|	Add "verilog_defines -list" and "verilog_defines -reset"	Clifford Wolf	2019-10-21	1	-0/+16
* \| \| \| \| \| \| \| \| \|	Fix handling of "restrict" in Verific front-end	Clifford Wolf	2019-10-21	1	-1/+1
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* \| \| \| \| \| \| \| \|	ecp5: Pass -nomfs to abc9	David Shah	2019-10-20	1	-2/+2
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* \| \| \| \| \| \| \|	Merge pull request #1457 from xobs/python-binary-name	Miodrag Milanović	2019-10-19	6	-9/+9
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\| * \| \| \| \| \| \| \|	Makefile: don't assume python is called `python3`	Sean Cross	2019-10-19	6	-9/+9
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* \| \| \| \| \| \| \|	Merge pull request #1454 from YosysHQ/mmicko/common_tests	Miodrag Milanović	2019-10-18	166	-1763/+455
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\| * \| \| \| \| \| \| \|	fixed error	Miodrag Milanovic	2019-10-18	1	-1/+1
\| * \| \| \| \| \| \| \|	Unify verilog style	Miodrag Milanovic	2019-10-18	11	-191/+157
\| * \| \| \| \| \| \| \|	Common memory test now shared	Miodrag Milanovic	2019-10-18	10	-89/+5
\| * \| \| \| \| \| \| \|	Remove not needed tests	Miodrag Milanovic	2019-10-18	4	-52/+0
\| * \| \| \| \| \| \| \|	Share common tests	Miodrag Milanovic	2019-10-18	103	-1316/+178
\| * \| \| \| \| \| \| \|	fix yosys path	Miodrag Milanovic	2019-10-18	1	-2/+2
\| * \| \| \| \| \| \| \|	Fix path to yosys	Miodrag Milanovic	2019-10-18	5	-5/+5
\| * \| \| \| \| \| \| \|	Moved all tests in arch sub directory	Miodrag Milanovic	2019-10-18	151	-5/+5
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* \| \| \| \| \| \| \|	Add async2sync	Miodrag Milanovic	2019-10-18	2	-8/+8
* \| \| \| \| \| \| \|	Merge pull request #1435 from YosysHQ/mmicko/efinix	Miodrag Milanović	2019-10-18	27	-1/+572
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\| * \ \ \ \ \ \ \	Merge branch 'master' into mmicko/efinix	Miodrag Milanović	2019-10-18	156	-896/+3156
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* \| \| \| \| \| \| \| \|	Merge pull request #1434 from YosysHQ/mmicko/anlogic	Miodrag Milanović	2019-10-18	21	-0/+430
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\| * \ \ \ \ \ \ \ \	Merge branch 'master' into mmicko/anlogic	Miodrag Milanović	2019-10-18	136	-896/+2726
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* \| \| \| \| \| \| \| \| \|	Merge pull request #1421 from YosysHQ/eddie/pr1352	Miodrag Milanović	2019-10-18	33	-0/+669
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\| * \ \ \ \ \ \ \ \ \	Merge branch 'master' into eddie/pr1352	Miodrag Milanović	2019-10-18	119	-987/+2470
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* \| \| \| \| \| \| \| \| \| \|	Merge pull request #1420 from YosysHQ/eddie/pr1363	Miodrag Milanović	2019-10-18	29	-47/+544
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\| * \| \| \| \| \| \| \| \| \|	hierarchy - proc reorder	Miodrag Milanovic	2019-10-18	10	-17/+21
\| * \| \| \| \| \| \| \| \| \|	Make equivalence work with latest master	Miodrag Milanovic	2019-10-17	3	-8/+8
\| * \| \| \| \| \| \| \| \| \|	remove not needed top module	Miodrag Milanovic	2019-10-17	2	-20/+2
\| * \| \| \| \| \| \| \| \| \|	remove not needed top module	Miodrag Milanovic	2019-10-17	2	-17/+2
\| * \| \| \| \| \| \| \| \| \|	split muxes synth per type	Miodrag Milanovic	2019-10-17	2	-39/+39
\| * \| \| \| \| \| \| \| \| \|	Test dffs separetely	Miodrag Milanovic	2019-10-17	2	-26/+19
\| * \| \| \| \| \| \| \| \| \|	Split latches into separete tests	Miodrag Milanovic	2019-10-17	2	-42/+27
\| * \| \| \| \| \| \| \| \| \|	Fix formatting	Miodrag Milanovic	2019-10-17	1	-1/+8
\| * \| \| \| \| \| \| \| \| \|	Clean verilog code from not used define block	Miodrag Milanovic	2019-10-17	2	-12/+0
\| * \| \| \| \| \| \| \| \| \|	Removed alu and div_mod test as agreed, ignore generated files	Miodrag Milanovic	2019-10-17	5	-70/+1
\| * \| \| \| \| \| \| \| \| \|	Test per flip-flop type	Miodrag Milanovic	2019-10-17	2	-47/+37
\| * \| \| \| \| \| \| \| \| \|	Add -assert	Eddie Hung	2019-10-17	1	-1/+1
\| * \| \| \| \| \| \| \| \| \|	Use built-in async2sync call as per #1417	Eddie Hung	2019-10-17	1	-4/+0
\| * \| \| \| \| \| \| \| \| \|	Update mul test to DSP48E1	Eddie Hung	2019-10-17	1	-9/+2
\| * \| \| \| \| \| \| \| \| \|	Update area for div_mod	Eddie Hung	2019-10-17	1	-6/+6
\| * \| \| \| \| \| \| \| \| \|	Add comment for lack of tristate logic pointing to #1225	Eddie Hung	2019-10-17	1	-1/+1
\| * \| \| \| \| \| \| \| \| \|	Move $x to end as 7f0eec8	Eddie Hung	2019-10-17	1	-1/+1
\| * \| \| \| \| \| \| \| \| \|	adffs test update (equiv_opt -multiclock)	SergeyDegtyar	2019-10-17	1	-5/+6
\| * \| \| \| \| \| \| \| \| \|	Fix div_mod test	Sergey	2019-10-17	1	-1/+1
\| * \| \| \| \| \| \| \| \| \|	Fix div_mod test	Sergey	2019-10-17	1	-1/+1
\| * \| \| \| \| \| \| \| \| \|	Fix div_mod test	Sergey	2019-10-17	1	-1/+1