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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 09:39:34 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:11:11 +0200 |
| commit | 1a399c6456b6ca7becf89a5c825b2c8d7b34dc3e (patch) | |
| tree | d9778b44d7879f6d66f8bcf6964db25c81c26bd6 | |
| parent | a198bcdd4ffe6b09787ea5bf2e69528ace375020 (diff) | |
| download | yosys-1a399c6456b6ca7becf89a5c825b2c8d7b34dc3e.tar.gz yosys-1a399c6456b6ca7becf89a5c825b2c8d7b34dc3e.tar.bz2 yosys-1a399c6456b6ca7becf89a5c825b2c8d7b34dc3e.zip | |
remove not needed top module
| -rw-r--r-- | tests/xilinx/tribuf.v | 15 | ||||
| -rw-r--r-- | tests/xilinx/tribuf.ys | 4 |
2 files changed, 2 insertions, 17 deletions
diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v index 75149d8ba..c64468253 100644 --- a/tests/xilinx/tribuf.v +++ b/tests/xilinx/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); always @(en or i) o <= (en)? i : 1'bZ; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index 696be2620..c9cfb8546 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -1,12 +1,12 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc tribuf flatten synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module # TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D |