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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:33:35 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:33:35 +0200 |
| commit | 12383f37b2e1d72784e01db0431efc8882f25430 (patch) | |
| tree | 5bd01531406aedd9ee9f1ceaaab18374a8235ec2 | |
| parent | 477702b8c91bb7780ac80b25c8ad659cd40b445d (diff) | |
| download | yosys-12383f37b2e1d72784e01db0431efc8882f25430.tar.gz yosys-12383f37b2e1d72784e01db0431efc8882f25430.tar.bz2 yosys-12383f37b2e1d72784e01db0431efc8882f25430.zip | |
Common memory test now shared
| -rw-r--r-- | tests/arch/anlogic/memory.ys | 2 | ||||
| -rw-r--r-- | tests/arch/common/memory.v (renamed from tests/arch/anlogic/memory.v) | 0 | ||||
| -rw-r--r-- | tests/arch/ecp5/memory.v | 21 | ||||
| -rw-r--r-- | tests/arch/ecp5/memory.ys | 2 | ||||
| -rw-r--r-- | tests/arch/efinix/memory.v | 21 | ||||
| -rw-r--r-- | tests/arch/efinix/memory.ys | 2 | ||||
| -rw-r--r-- | tests/arch/ice40/memory.v | 21 | ||||
| -rw-r--r-- | tests/arch/ice40/memory.ys | 2 | ||||
| -rw-r--r-- | tests/arch/xilinx/memory.v | 21 | ||||
| -rw-r--r-- | tests/arch/xilinx/memory.ys | 2 |
10 files changed, 5 insertions, 89 deletions
diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys index 8c0ce844e..87b93c2fe 100644 --- a/tests/arch/anlogic/memory.ys +++ b/tests/arch/anlogic/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/anlogic/memory.v b/tests/arch/common/memory.v index cb7753f7b..cb7753f7b 100644 --- a/tests/arch/anlogic/memory.v +++ b/tests/arch/common/memory.v diff --git a/tests/arch/ecp5/memory.v b/tests/arch/ecp5/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/ecp5/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/ecp5/memory.ys b/tests/arch/ecp5/memory.ys index 9b475f122..c82b7b405 100644 --- a/tests/arch/ecp5/memory.ys +++ b/tests/arch/ecp5/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/efinix/memory.v b/tests/arch/efinix/memory.v deleted file mode 100644 index 5634d6507..000000000 --- a/tests/arch/efinix/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [8:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/memory.ys index fe24b0a9b..6f6acdcde 100644 --- a/tests/arch/efinix/memory.ys +++ b/tests/arch/efinix/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/ice40/memory.v b/tests/arch/ice40/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/ice40/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/memory.ys index a66afbae6..c356e67fb 100644 --- a/tests/arch/ice40/memory.ys +++ b/tests/arch/ice40/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/xilinx/memory.v b/tests/arch/xilinx/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/xilinx/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys index 5402513a2..da1ed0e49 100644 --- a/tests/arch/xilinx/memory.ys +++ b/tests/arch/xilinx/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap |