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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 13:15:36 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 13:15:36 +0200 |
| commit | 190b40341abd73ab5edf0e6740b6526e9575253b (patch) | |
| tree | 971fae1a1b7d3204827759454fa55accdc9bc01f | |
| parent | 9bd9db56c8ef8ca413f97086fd53609c50df343b (diff) | |
| download | yosys-190b40341abd73ab5edf0e6740b6526e9575253b.tar.gz yosys-190b40341abd73ab5edf0e6740b6526e9575253b.tar.bz2 yosys-190b40341abd73ab5edf0e6740b6526e9575253b.zip | |
fixed error
| -rw-r--r-- | tests/arch/common/counter.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v index 97604d3d8..9746fd701 100644 --- a/tests/arch/common/counter.v +++ b/tests/arch/common/counter.v @@ -6,6 +6,6 @@ module top ( out, clk, reset ); always @(posedge clk, posedge reset)
if (reset)
out <= 8'b0;
- end
+ else
out <= out + 1;
endmodule
|